FIELD OF THE INVENTION
The invention relates to a CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, including a first field effect transistor of a first conduction type and a second field effect transistor of a second conduction type having load paths being connected in series between a supply voltage terminal and a reference potential terminal, the first value or the second value of the supply voltage being selectively applied to the supply voltage terminal during operation, and an input terminal being connected to gate terminals of the two field effect transistors.
CMOS input stages have been known for a long time and are described in detail in the book entitled: Halbleiter-schaltungstechnik [Semiconductor Circuitry] by Tietze and Schenk, 8th Edition, 1986, page 211 ff., for instance. FIG. 9.36 thereof shows a CMOS inverter that is constructed as such an input stage. Depending on the input voltage, the output voltage of the inverter is equal to either the supply voltage V.sub.DD or ground, because one of the transistors T1 or T2 is always made conducting.
In order to assure the lowest possible failure rates, integrated circuits are run in what is known as a burn-in mode after their manufacture. Such a burn-in mode guarantees that so-called premature failures will be recognized as early as possible by means of simulated aging. In the burn-in mode, the integrated circuits are operated at an elevated voltage, such as 8 V. That sets an accelerated aging process in motion, and the aforementioned premature failures can thus be recognized very quickly.
One problem in such an operating mode is that with the elevation of the supply voltage, the thresholds of the input stages are also increased. Particularly in components that are operated externally at 5 V and internally at 3.3 V, for instance, the burn-in is performed in a test mode, in which the regulators are turned off in order to reduce the external supply voltage to 3.3 V. As a result the internal supply voltage becomes equal to the external supply voltage. If a component has that test option, it cannot be assured that the component will not unintentionally jump to that test mode when it is turned on. If that happens, then because of the shift in thresholds of the input stages, the component can no longer, as specified, be put into a basic state with a TTL level at an application control input, because a logical "high" at an input is no longer recognized. In memory components, the control input is RAS, for instance, and the basic state is established by eight RAS-only cycles, for example.